Field of the Invention
The present invention relates to a method of manufacturing a package, a package, and a multi-package preform.
Description of the Related Art
Packages may be denoted as encapsulated electronic chips with electrical connects extending out of the encapsulant and being mounted to an electronic periphery, for instance on a printed circuit board. Packaging cost is an important driver for the industry. Related with this are performance, dimensions and reliability. The different packaging solutions are manifold and have to address the needs of the application. There are applications, where high performance is required, others, where reliability is the top priority—but all requires lowest possible cost.
US 2013/299848 A1 discloses a semiconductor package which includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.